1. Field of the Invnetion
The present invention relates to an interface between a radio frequency (RF) signal processing integrated circuit and a base band processor. In particular, the present invention relates to an interface between an RF signal processing integrated circuit for a global positioning system (GPS) application and a base band processor that is implemented by a general purpose digital signal processor or a general purpose microprocessor of a mobile device.
2. Discussion of the Related Art
A GPS receiver typically includes an RF “front end” integrated circuit (RFIC) and a digital signal processing integrated circuit (“base band processor”). This base band processor is often implemented in an application specific integrated circuit (ASIC) or programmed into one or more field programmable gate arrays (FPGAs). The RF IC receives signals from the GPS satellites through an antenna, down-converts the GPS signals to an intermediate frequency, filters the down-converted signals and digitizes the filtered signal at a prescribed sampling data rate. The RFIC then provides the digitized samples to the base band processor, which “acquires” (i.e., detects) from the digitized samples the signals of one or more GPS satellites (“acquired satellites”). The signals of the acquired satellites are then used to compute the distance (“range”) between the receiver and each acquired satellite. The ranges of the acquired satellites may then be used to determine the position of the receiver.
Until recently, the base band processor is often a special purpose integrated circuit specifically designed to be used for the required high speed digital signal processing in GPS applications (e.g., a correlation engine), and may include both hardware and software components. The signal of each GPS satellite is characterized by a unique code vector modulating a carrier signal. In one implementation, the code vector is a 1023-bit pseudorandom noise or code which is repeated every millisecond (i.e., at a “chipping” rate of 1.023 MHz). Conventionally, a common frequency fo=1.023 MHz, which is a common divisor of the two GPS frequencies 1575.42 MHz and 1227.6 MHz, is used as a design parameter for GPS applications. In the prior art, an intermediate frequency of 4fo is typically used, which requires a sampling rate of 16fo to avoid artifacts due to aliasing. Thus, in the prior art, the sampling rate is typically provided at 16fo. At a 2-bit or a 3-bit sample resolution (i.e., a sign bit plus one or two magnitude bits per sample), the digitized samples are delivered to the digital signal processing integrated circuit at a bit rate of at least 32-48 megabits per second (Mbs).
Due to this high sample rate required to support successful satellite acquisitions, a general purpose microprocessor or an off-the-shelf (i.e., industry standard) digital signal processor is not used because the simple industry standard serial data interface or interfaces of a general purpose microprocessor do not support the required high date rate of 32-48 Mbs. Even though there are complex high speed data interfaces in such a general purpose processor, these complex interfaces require the RF IC to have significant interface logic resources. Thus, in the prior art, a custom-designed signal processing integrated circuit is preferred as the base-band processor for the GPS signals. Typically, such a custom-designed signal processing integrated circuit uses a special purpose data interface to handle the high data rate continuous data transfers from the RF IC.